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AN171
AB1 P R O T O T Y P I N G B O A R D U S E R ’ S G U I D E
1.0. Summary
The AB1 prototyping board provides a 3 x 3.75" prototyping area (0.1" center through-hole) with access to all MCU
I/O signals. Access to I/O signals is provided by a 96-pin, high density connector that mates directly to the expan-
sion connector of C8051F020-TB, C8051F040-TB, C8051F060-TB, and C8051F120-TB target boards. A 128 kB
SRAM is installed on the board which can be connected to the MCU's External Memory Interface by installing a
single 2-pin jumper (included).
2.0 Features
96 pin 3 row connector
128 kB SRAM Part number IDT71V124
SRAM disable jumper J1(open = disabled , closed = enabled )
Duplicate of connector pins for easy access to signals
Digital and analog supply and ground rails
3.0 SRAM Details
The IDT71V124SA12PH is a high-speed with 12 nanosecond access and cycle time static SRAM. For more further
information on access and cycle times for this SRAM please refer to the IDT71V124 data sheet available at http://
www.idt.com/docs/71V124SA_DS_30147.pdf . To enable the SRAM jumper J1 must be installed and the /CS
Chip Select pin must be pulled low. The SRAM utilizes the External Memory Interface from F02X and later
devices, more information on using this interface can be found in Section 16 of the C8051F02x Data Sheet. When
enabled the SRAM uses ports 5, 6, and 7 and the upper nibble of port 4. The pin-out is as follows:
Signal Name
SRAM Pin(s)
C8051F02XTB
Description
Connection
/WE
/CS
/OE
VDD
GND
I/O0…I/O7
A0…A7
A8...A15
A16
12
5
28
8,24
9,25
6,7,10,11,22,23,26,27
1,2,3,4,13,14,15,16
17,18,19,20,21,29,30,31
32
P4.7
P4.4(J1 closed)
P4.6
+3 VD
GND
P7.0…P7.7
P6.0…P6.7
P5.0…P5.7
P4.5
Write Enable
Chip Select
Output Enable
Digital Power
Digital Ground
Data Bus
Address Bus Low Byte
Address Bus High Byte
Bank Select
Rev. 0.3 1/04
Copyright ? 2004 by Silicon Laboratories
AN171
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